The present invention relates to a method of improving imprint lithography alignment as well as a system and template to be used for same. The method, system, and template herein described have particular utility in subfield alignment of sub 100 nm features requiring registration of about 25 nm.
Micro-fabrication involves the fabrication of very small structures, e.g., having features on the order of micrometers or smaller. One industry that has been driving the fabrication of increasingly smaller structures is the electronics industry. As electronic devices have become smaller and faster, the integrated circuits that drive them have necessarily become smaller.
A technique known as ‘photolithography’, or simply ‘lithography’, is typically employed in the manufacture of integrated circuits. Lithographic techniques are generally used to pattern the various levels of an integrated circuit. Typically, these lithographic techniques include applying a photosensitive material to a semiconductor substrate. These photosensitive materials, commonly referred to as “resist,” are selectively exposed to a form of radiation. An exposure tool and photomask are often used to obtain the desired selective exposure. Such exposure changes the solubility of the resist such that the photomask's pattern is formed in the resist following a development process to remove the soluble resist. The resulting patterned resist serves to protect underlying conductive or dielectric material from etching or ion implantation.
It is critical to align successive layers of an integrated circuit to each other to ensure proper operation of the circuit. In particular, the photomask pattern must be properly aligned to previously formed semiconductor topography features during the lithography process. In the extreme, lithographic misalignment may lead to shorting between structures that should be isolated from each other, and isolation of structures that should be coupled to each other.
Imprint lithography is capable of manufacturably producing sub-100 nm features. Several imprint lithography techniques have been investigated as low cost, high volume manufacturing alternatives to conventional photolithography for high-resolution patterning. In this emergent technology, a relief image in a template is used to replicate a surface relief into a polymerizable material arranged upon the surface of a substrate. The template makes mechanical contact with the material arranged upon the substrate, and the material is subjected to conditions to solidify and/or to polymerize the same such that a relief structure complimentary to that of the template is formed on the substrate. The material may be solidified or polymerized by, for example, heat or actinic light. Such patterning and polymerization techniques may be referred to as thermal imprint lithography or ultraviolet (‘UV’) imprint lithography, respectively. Typical substrates may include semiconductors, dielectric materials, magnetic materials, or optoelectronic materials.
Imprint lithography may be used in wide variety of applications. That is, imprint lithography applications are not limited to the manufacture of integrated circuits. However, typical applications require alignment of subsequently imprinted device layers to previously imprinted device layers. Properly aligning subsequent imprint lithography device layers becomes increasingly difficult as feature sizes become ever smaller. Imprint lithography systems are currently capable of printing features in the sub-100 nm range with a 3σ overlay alignment capability of less than about 500 nm. Despite a high degree of alignment accuracy, current imprint lithography systems are challenged by the degree of precision required to consistently align multiple layers having minimum feature sizes. Devices having such minimum feature sizes may also have registration tolerances of about 25 nm or less. Consequently, proper alignment of multi-layered devices having minimum feature sizes may be a relatively infrequent event. It is desired, therefore, to provide improvement to imprint lithography alignment.